Processing systems often require the rapid transfer of data between a plurality of integrated circuits (ICs). As computing processes continue to increase in complexity, various processing systems have deployed processing elements to handle ever increasing complexity and volume of computations. For example, the processing elements can be central processing units (CPUs) and the like. As the speed of the processing elements increases, the speed of the interface between the ICs must also increase to avoid becoming a limiting constraint.
However, one important aspect of the interface is the proper time alignment between two ICs (e.g., a transmitting device and a receiving device). More specifically, when data is passed between the two ICs, they need to be properly aligned so that a sampling clock, e.g., a rising edge and/or a falling edge of the sampling clock, of the receiving device will be properly aligned to sample or capture the data when it is presented to the receiving device.
Although the transmitting device and the receiving device can be initially aligned, e.g., via the use of training samples, the time alignment can change over time due to drift. Many factors can contribute to the increase or decrease of drift, e.g., changing temperature or changing supply voltage. As such, if the time alignment is not dynamically maintained during the operation of the transmitting device and the receiving device, then there is a possibility that the sampling clock of the receiving device will become misaligned and the wrong data will be captured by the receiving device.